Various new types of power devices have emerged along with the development of very large-scale integrated circuits, where the most representative device is a trench-type Vertical Double-diffused Metal Oxide Semiconductor transistor (VDMOS). The VDMOS transistor is an ideal power device in both a switch application and a linear application. Consequently the VDMOS transistor has been widely applied in various fields, e.g., an electronic speed-adjuster, an inverter, a switch power source, an electronic power, a high-fidelity audio system, an electronic ballast, etc. GOI detection is an important step of evaluating the quality of a formed gate oxide layer in a VDMOS fabrication process.
In the prior art, GOI detection on the VDMOS is typically performed by fabricating a GOI silicon wafer and then performing GOI detection on the fabricated GOI silicon wafer. Particularly the GOI silicon wafer needs to be fabricated by growing a gate oxide layer separately on a silicon substrate and then growing a poly-silicon layer on the surface of the grown gate oxide layer to thereby form the GOI silicon wafer. Voltage is applied respectively across the poly-silicon layer and the silicon substrate through the formed GOI silicon wafer to perform a GOI test, and the quality of the gate oxide layer is evaluated from the breakthrough voltage of the resulting oxide layer. In order to ensure test data to be closer to a real condition of the VDMOS device, some patterns may be designed for fabrication of the GOI silicon wafer so that the designed patterns are etched on the silicon substrate through masks and then the gate oxide layer and the poly-silicon layer are grown in that order. In a particular implementation, the different patterns formed on the silicon substrate need the different masks corresponding thereto, and these masks can be referred to as GOI masks, and then corresponding pattern structures are fabricated on the silicon substrate.
In the prior art, a large number of masks have to be fabricated for fabrication of the GOI silicon wafer and consequently have some resource wasted, and required repeated alignment of the different masks may incur a considerable error between the fabricated GOI silicon wafer and the VDMOS device and hence lower the accuracy in a result of detecting the GOI silicon wafer.